CMS Muon Endcap ALCT Delay chips D16G Mass Production Test and Delivery

blue_ball.gif Introduction.
The 16 channel delay chips D16G ( Ref. 1) provide programmable time delay of the ALCT ( Ref. 2) input signals coming from the CMS muon endcap CSC anode front end boards. Here we present the status and results of the mass production test of these chips. The status of chips delivery to UCLA for ALCT boards assembly is given as well. This page helps to monitor the performance of the delay chips. It also provides information needed for the tuning parameters of the chips installed on the ALCT board. The parameters of the chip were measured at Uc=0 mV.
Description of the distributions of the delay chip parameters in Fig. 1 (before applying selection cuts) given in Table 1 is here. The cuts are shown as red lines.For chips from trays 1-16 we used cuts from Cut List #4 and starting from tray 17 - Cut List #5. Also, starting from tray 17, the data have been analyzing online on the delay chips test stand. The chips that passed the selection cuts have parameters distributions given in Fig.2. The overall status of the test presented in Fig.3.
Due to spread of the parameters the delay chips were divided on 9 groups having each 2 ns wide bin in the averaged over chip delay(code=15) distribution (Page 5 in Fig.2). As an example for the chips from trays 1-16 the list of the groups is given here. In this list D0 is the averaged over all chips in the group delay at code 0, delay(0), D15 - the same for delay(15). SLP is the slope as (D15-D0)/15, MxD is the maximum absolute deviation of the delay in the group from predicted delay defined as D0 + Code*SLP where the Code is the delay code (0-15). MxW is the maximum width of the road (delays of all channels from all chips in the group at given delay code) over all delay codes. All delays are absolute delays in the chips (the test stand delays were subtracted). The chips from groups with numbers less than 8 can be tuned on the ALCT board after assembling to get the same average delay at code of 15 as in group #8. Increasing the Uc voltage by 50 mV raises D15 by 0.8-1.1 ns. The chips from groups 1,2 and 9 (of total about 10%) will not be used for installation on the ALCT boards. Table 2 presents the distributions of the parameters for each group.
The total number available for the test chips was 23,515 (trays 1-149). They were tested in the first pass. Chips in tray 150 and beyond are the chips which failed in the first pass and have been remeasured.
The time stability of the delay chips test stand is shown in Table 3. The first page has the plots of relative changes in the averaged for each tray chip delays at the delay code of 0 (in slot 1 and 2). The second page shows stability of residuals for each channel.
Table 4 is monitoring the delivery schedule of the chips from each group.
blue_ball.gif Table 1. Status and results of the test.

Date Tray ## Before cuts After cuts Test status Chips tested Passed the cuts Yield, %
11/01/2001 - 07/10/2002 1 - 154 Fig. 1* Fig. 2 Fig. 3* 23515* 20405 87%

* - does not include remeasured chips, trays 150-154

blue_ball.gif Table 2. Group distributions (Fig.).

Group # 1 2 3 4 5 6 7 8 9
Fig. # 1 2 3 4 5 6 7 8 9
Quantity 428 659 1273 1863 2261 3118 6297 3948 556
Yield, % 1.8% 2.8% 5.4% 7.9% 9.6% 13.3% 26.8% 16.8% 2.4%


blue_ball.gif The uniformity of the channels within each certified chip.
The channel uniformity is shown using the channel residual which is defined as the difference between the channel parameter and its value averaged over the 16 channels of each chip, see it in ( Uniformity ). It is one and the same for all groups.

blue_ball.gif Table 3. Time stability of the test (by trays).

Date Tray ## Plot
11/01/2001 - 07/05/2002 1 - 149 Fig.

blue_ball.gif Table 4. Delivery to the UCLA (for the ALCT assembly) and other sites.

Site Shipment Date Number of chips,total Group 3 Group 4 Group 5 Group 6 Group 7 Group 8 Group 9
UCLA 1 11/14/2001 1120       320 480 320  
  2 02/22/2002 960         640 320  
  3 05/01/2002 5760     960 960 2880 960  
  4 06/06/2002 3840     960 960 960 960  
  5 07/15/2002 4258     335 923 1498 1502  
  6 11/11/2004 479             479
  Total*   16417     2255 3163 6458 4062 479
TOTEM 1 10/28/2003 87             87
  Total*   87             87
Total     16504     2255 3163 6458 4062 566

* - Groups 6-9 have more chips than given in Table 2 because the files with data for the corresponding balance of chips (about 1.5 % of the total) were not provided by the delay test stand for the presentation in Table 2. Also contradiction with Table 2 for group #5 remains unexplained. The final numbers (see total and table 5 below) are:

23716 - total number of tested chips.
20811 - total number of certified chips (corresponding yield is 88%).

blue_ball.gif Table 5. Group distributions (final numbers)

Group # 1 2 3 4 5 6 7 8 9 Total
Quantity 452 680 1280 1895 2255 3163 6458 4062 566 20811


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Last modified: Thu Nov. 11 12:30:00 CST 2004