For the CMS Endcap Muon Electronics System Review at CERN, 09/18/00.
Text.

esr4.ps - Text in *.ps format (without figures, only tables at the end, Fig.1-9 are below)

esr4.tex - Latex source text

Figures.

Fig 1. - The anode front-end electronics structure (one channel).

Fig 2. - The anode amplifier-discriminator structure (one channel).

Fig 3. - The anode amplifier-discriminator functional circuit diagram (one channel).

Fig 4. - The AD16 board diagram.

Fig 5. - The AD16 board assembly diagram.

Fig 6. - The AD16 board circuit diagram with input and output connectors specifications.

Fig 7. - The AD16 board position on chamber.

Fig 8. - The structure of one channel of the delay chip.

Fig 9. - The interface structure of one channel of the delay chip.

Attachment 1. List of circuit diagrams for chip CMP16F.

Fig 1. - CMP16F chip (cmp16_f.ps 134 Kb)

Fig 2. - one channel scheme (asd04_f.ps 24 Kb)

Fig 3. - preamplifier and tail cancellation circuit (ampl04_f.ps 28 Kb)

Fig 4. - two pole shaper, zero-crossing shaper (shaper15.ps 65 Kb)

Fig 5. - two thresholds discriminator (discr_15.ps 39 Kb)

Fig 6. - LVDS compatible output buffer (Out_buf.ps 60 Kb)

Fig 7. - charge sensitive amplifier (pamp_15b.ps 34 Kb)

Fig 8. - general use wide range amplifier (wr_sh31.ps 27 Kb)

Fig 9. - wide range amplifier with differential output (wr_sh32.ps 38 Kb)

Fig 10. - wide range amplifier modification (OP1.ps 28 Kb)

Fig 11. - amplifier-integrator N-MOS (wrampi21.ps 31 Kb)

Fig 12. - amplifier integrator P-MOS (wraint_p.ps 30 Kb)

Fig 13. - enable high threshold discriminator (HTD_f.ps 49 Kb)

Fig 14. - precision time discriminator (zero threshold) (PTD.ps 42 Kb)

Fig 15. - NPN stage follower for test channel (NPN_flw.ps 24 Kb)

Fig 16. - CMOS equivalent resistor 30K (MR30k.ps 11 Kb)

Fig 17. - CMOS equivalent resistor 75K (MR75k.ps 15 Kb)

Fig 18. - chip layout (CMP16_F_chip.ps 873 Kb)

Fig 19. - complete layout of the chip (CMP16_f_lo.eps 7301 Kb)

Attachment 2. Delay chip circuit diagrams

Fig 1. - chip scheme (Del16.ps 56 Kb)

Fig 2. - delay channel scheme (del_chan.ps 69 Kb)

Fig 3. - serial data interface (control.ps 52 Kb)

Fig 4. - delay monostable (del_monost.ps 26 Kb)

Fig 5. - output pulse monostable (monost.ps 24 Kb)

Fig 6. - LVDS to CMOS level converter (LVDS_TTL.ps 59 Kb)

Fig 7. - flip-flop (DFFC.ps 153 Kb)

Fig 8. - input pad (pad_inp.ps 84 Kb)

Fig 9. - output pad (pad_out.ps 82 Kb)

Fig 10. - bi-directional pad (pad_bidir.ps 86 Kb)

Fig 11. - chip layout (del16chip.ps 860 Kb)

Fig 12. - complete layout (del16_lo.eps 2709 Kb)

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Last modified: Wed Aug 23 14:40:00 CST 2000 bondar@fnal.gov teren@fnal.gov